AMD Memory Tweak Tool — это утилита с графическим интерфейсом на базе Windows и Linux, которая позволяет не только разогнать память видеокарты AMD Radeon на лету, но и позволяет настроить тайминги памяти. 5b6c6p
Большинство таймингов применяются в реальном времени, в то время как ваша машина работает в Windows / Linux GUI, некоторые требуют переобучения памяти через перезагрузку, что означает, что они не могут быть изменены в это время, потому что перезагрузка сбрасывает тайминги к значениям по умолчанию.
Пока вы работаете, инструмент также позволяет играть с частотой ядра графического процессора и управлением вентиляторами.
AMD Memory Tweak поддерживает как Windows, так и Linux (GUI) и работает со всеми последними графическими процессорами AMD Radeon с типами памяти GDDR5 и HBM2.
Для Windows требуется Radeon Software Adrenalin 19.4.1 или v19.5. * или ROCM amdgpu-pro для активной работы с GPU в случае Linux. Кроме того, версия для Linux имеет некоторые зависимости, такие как pciutils-dev, libpci-dev, build-essential и git.
Использование и инструкции AMD Memory Tweak 5id72
Global command line options 6i2k1g
| Command | Input | Extra Info |
|---|---|---|
| — -help | Show this output | |
| — -version|—v | Show version info | |
| — -gpu|- -i | Comma-Seperated gpu indices | Selected device(s) |
| — -current | List current twiming values |
Command line options: (HBM2) 32h44
| Command | Input | Extra Info |
|---|---|---|
| — -CL|- -cl | [value] | Cas Latency |
| — -RAS|- -ras | [value] | Active to PRECHARGE command period |
| — -RCDRD|- -rcdrd | [value] | Active to READ command delay |
| — -RCDWR|- -rcdwr | [value] | Active to WRITE command delay |
| — -RC|- -rc | [value] | Active to Active command period |
| — -RP|- -rp | [value] | Precharge command period |
| — -RRDS|- -rrds | [value] | Active bank A to Active or Single bank Refresh bank B command delay different bank group |
| — -RRDL|- -rrdl | [value] | Active bank A to Active or Single Bank Refresh bank B command delay same bank group |
| — -RTP|- -rtp | [value] | Read to precharge delay |
| — -FAW|- -faw | [value] | Four Active Window |
| — -CWL|- -cwl | [value] | |
| — -WTRS|- -wtrs | [value] | Write to read delay |
| — -WTRL|- -wtrl | [value] | tWTR = tWTRL when bank groups is enabled and both WRITE and READ |
| — -WR|- -wr | [value] | Write Recovery Time |
| — -RREFD|- -rrefd | [value] | |
| — -RDRDDD|- -rdrddd | [value] | |
| — -RDRDSD|- -rdrdsd | [value] | |
| — -RDRDSC|- -rdrdsc | [value] | |
| — -RDRDSCL|- -rdrdscl | [value] | |
| — -WRWRDD|- -wrwrdd | [value] | |
| — -WRWRSD|- -wrwrsd | [value] | |
| — -WRWRSC|- -wrwrsc | [value] | |
| — -WRWRSCL|- -wrwrscl | [value] | |
| — -WRRD|- -wrrd | [value] | |
| — -RDWR|- -rdwr | [value] | |
| — -REF|- -ref | [value] | Average Periodic Refresh Interval |
| — -MRD|- -mrd | [value] | Mode Set command cycle time |
| — -MOD|- -mod | [value] | Mode Set command update delay |
| — -XS|- -xs | [value] | Self refresh exit period |
| — -XSMRS|- -xsmrs | [value] | |
| — -PD|- -pd | [value] | Power down entry to exit time |
| — -CKSRE|- -cksre | [value] | Valid CK Clock required after self refresh or power-down entry |
| — -CKSRX|- -cksrx | [value] | Valid CK Clock required before self refresh power down exit |
| — -RFB|- -rfb | [value] | |
| — -STAG|- -stag | [value] | |
| — -XP|- -xp | [value] | |
| — -DED|- -ded | [value] | |
| — -CKE|- -cke | [value] | |
| — -RDDATA|- -rddata | [value] | |
| — -WRLAT|- -wrlat | [value] | |
| — -RDLAT|- -rdlat | [value] | |
| — -WRDATA|- -wrdata | [value] | |
| — -CKESTAG|- -ckestag | [value] | |
| — -RFC|- -rfc | [value] | Auto Refresh Row Cycle Time |
Command line options: (HBM) 5m2b3u
| Command | Input | Extra Info |
|---|---|---|
| — -CKSRE|- -cksre | [value] | |
| — -CKSRX|- -cksrx | [value] | |
| — -CKE_PULSE|- -cke_pulse | [value] | |
| — -CKE|- -cke | [value] | |
| — -SEQ_IDLE|- -seq_idle | [value] | |
| — -CL|- -cl | [value] | CAS to data return latency |
| — -W2R|- -w2r | [value] | Write to read turn |
| — -R2R|- -r2r | [value] | Read to read time |
| — -CCDL|- -ccdl | [value] | Cycles between r/w from bank A to r/w bank B |
| — -R2W|- -r2w | [value] | Read to write turn |
| — -NOPR|- -nopr | [value] | Extra cycle(s) between successive read bursts |
| — -NOPW|- -nopw | [value] | Extra cycle(s) between successive write bursts |
| — -RCDW|- -rcdw | [value] | # of cycles from active to write |
| — -RCDWA|- -rcdwa | [value] | # of cycles from active to write with auto-precharge |
| — -RCDR|- -rcdr | [value] | # of cycles from active to read |
| — -RCDRA|- -rcdra | [value] | # of cycles from active to read with auto-precharge |
| — -RRD|- -rrd | [value] | # of cycles from active bank a to active bank b |
| — -RC|- -rc | [value] | # of cycles from active to active/auto refresh |
| — -MRD|- -mrd | [value] | |
| — -RRDL|- -rrdl | [value] | |
| — -RFC|- -rfc | [value] | Auto-refresh command period |
| — -TRP|- -trp | [value] | Precharge command period |
| — -RP_WRA|- -rp_wra | [value] | From write with auto-precharge to active |
| — -RP_RDA|- -rp_rda | [value] | From read with auto-precharge to active |
| — -WDATATR|- -wdatatr | [value] | |
| — -T32AW|- -t32aw | [value] | |
| — -CRCWL|- -crcwl | [value] | |
| — -CRCRL|- -crcrl | [value] | |
| — -FAW|- -faw | [value] | |
| — -PA2WDATA|- -pa2wdata | [value] | |
| — -PA2RDATA|- -pa2rdata | [value] | |
| — -REF|- -ref | [value] | Refresh Rate |
| — -ENB|- -enb | [value] | |
| — -CNT|- -cnt | [value] | |
| — -TRC|- -trc | [value] |
Command line options: (GDDR5) 1z2h2c
| Command | Input | Extra Info |
|---|---|---|
| — -CKSRE|- -cksre | [value] | |
| — -CKSRX|- -cksrx | [value] | |
| — -CKE_PULSE|- -cke_pulse | [value] | |
| — -CKE|- -cke | [value] | |
| — -SEQ_IDLE|- -seq_idle | [value] | |
| — -CL|- -cl | [value] | CAS to data return latency |
| — -W2R|- -w2r | [value] | Write to read turn |
| — -R2R|- -r2r | [value] | Read to read time |
| — -CCDL|- -ccdl | [value] | Cycles between r/w from bank A to r/w bank B |
| — -R2W|- -r2w | [value] | Read to write turn |
| — -NOPR|- -nopr | [value] | Extra cycle(s) between successive read bursts |
| — -NOPW|- -nopw | [value] | Extra cycle(s) between successive write bursts |
| — -RCDW|- -rcdw | [value] | # of cycles from active to write |
| — -RCDWA|- -rcdwa | [value] | # of cycles from active to write with auto-precharge |
| — -RCDR|- -rcdr | [value] | # of cycles from active to read |
| — -RCDRA|- -rcdra | [value] | # of cycles from active to read with auto-precharge |
| — -RRD|- -rrd | [value] | # of cycles from active bank a to active bank b |
| — -RC|- -rc | [value] | # of cycles from active to active/auto refresh |
| — -RFC|- -rfc | [value] | Auto-refresh command period |
| — -TRP|- -trp | [value] | Precharge command period |
| — -RP_WRA|- -rp_wra | [value] | From write with auto-precharge to active |
| — -RP_RDA|- -rp_rda | [value] | From read with auto-precharge to active |
| — -WDATATR|- -wdatatr | [value] | |
| — -T32AW|- -t32aw | [value] | |
| — -CRCWL|- -crcwl | [value] | |
| — -CRCRL|- -crcrl | [value] | |
| — -FAW|- -faw | [value] | |
| — -PA2WDATA|- -pa2wdata | [value] | |
| — -PA2RDATA|- -pa2rdata | [value] | |
| — -RAS|- -ras | [value] | |
| — -ACTRD|- -actrd | [value] | |
| — -ACTWR|- -actwr | [value] | |
| — -RASMACTRD|- -rasmactrd | [value] | |
| — -RASMACWTR|- -rasmacwtr | [value] | |
| — -RAS2RAS|- -ras2ras | [value] | |
| — -RP|- -rp | [value] | |
| — -WRPLUSRP|- -wrplusrp | [value] | |
| — -BUS_TURN|- -bus_turn | [value] | |
| — -REF|- -ref | [value] | Refresh Rate |